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MCP3464T-E/ST Datasheet(PDF) 37 Page - Microchip Technology

Part # MCP3464T-E/ST
Description  Two/Four/Eight-Channel, 153.6 ksps, Low Noise, 16-Bit Delta-Sigma ADC
PDF  108 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3464T-E/ST Datasheet(HTML) 37 Page - Microchip Technology

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 2019-2021 Microchip Technology Inc.
DS20006180D-page 37
MCP3461/2/4
FIGURE 5-3:
MDAT Serial Outputs in
Function of the Modulator Output Code.
5.4.3
BOOST MODES
The Delta-Sigma modulator includes a programmable
biasing circuit in order to further adjust the power
consumption to the sampling speed applied through
the MCLK. This can be programmed through the
BOOST[1:0] bits in the CONFIG2 register. The
different BOOST settings are applied to the whole
modulator circuit, including the voltage reference
buffers. The settings of the BOOST[1:0] bits are
described in Table 5-5.
The maximum achievable Analog Master Clock (AMCLK)
speed, the maximum sampling frequency (DMCLK)
and the maximum achievable data rate (DRCLK) are
highly dependent on the BOOST[1:0] and GAIN[2:0]
settings. A higher BOOST setting will allow the circuits’
bandwidth to be increased and will allow a higher
analog master clock rate that will then increase the
baseband of the input signals to be converted. The
digital gain (that is enabled at 32x and 64x gains) has
no influence on the achievable bandwidth.
A typical dependency of the bandwidth in relation to the
GAIN for each BOOST setting combination is shown in
Figure 2-20 to Figure 2-23. Typically, a larger GAIN
setting requires a higher BOOST setting in order to
achieve the same bandwidth performance.
Figure 2-24 shows the behavior of the achievable
bandwidth at BOOST = 1x with AVDD corner cases.
Since the BOOST settings vary, the internal slew rate
of the modulator components using a lower VREF value
will improve the bandwidth if low BOOST settings are
used and are showing a limited bandwidth behavior.
TABLE 5-4:
DELTA-SIGMA MODULATOR
OUTPUT BIT STREAM CODING
COMP[3:0]
Code
Modulator
Output Code
(Decimal)
MDAT
Serial
Stream
Equivalent
VREF
Voltage
1111
+2
1111
+VREF
0111
+1
0111
+VREF/2
0011
0
0011
0
0001
-1
0001
-VREF/2
0000
-2
0000
-VREF
AMCLK
tDOMDAT
MDAT
(code = +2)
MDAT
(code = +1)
MDAT
(code = 0)
MDAT
(code = -1)
MDAT
(code = -2)
COMP[3]
C OMP[2]
COMP[1]
C OMP[0]
tDOMDAT tDOMDAT tDOMDAT tDOMDAT
TABLE 5-5:
BOOST SETTINGS
DESCRIPTION
BOOST[1:0]
Bias Current
00
x0.5
01
x0.66
10
x1 (default)
11
x2



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