PIMXRT516SCVP5A datasheet(30/124 Pages) NXP

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i.MX RT1160 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 04/2021

NXP Semiconductors

Electrical characteristics

Set Point #9

Active

• CM7 is clock gated, lower voltage to 0.9 V; CM4

runs at 100 MHz, lower voltage to 0.9 V

• CM4 domain bus frequency at 50 MHz

• Enables ECC for cache, TCM, and OCRAM

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• 16 MHz, 400 MHz, and external 32 kHz crystal

are enabled

• All PLLs are power gated

• All peripherals controlled by CM7 core are clock

gated, but remain powered

DCDC_IN

14.5

39.5

VDD_LPSR_IN

28.2

30.2

A

VDD_SNVS_IN

3.9

A

Total

47.956

130.486

Set Point

#11 Active

• CM7 is power off; CM4 runs at 200 MHz, drive

voltage to 1.0 V

• CM4 domain bus frequency at 100 MHz

• Enables ECC for CM4 TCM and OCRAM

• DCDC is off, LDO_LPSR_ANA and

LDO_LPSR_DIG are active

• 16 MHz, 400 MHz, and external 32 kHz crystal

are enabled

• All PLLs are power gated

• The WAKEUPMIX domain, MEGAMIX domain,

and DISPLAYMIX domain are power gated

• All peripherals in LPSRMIX domain are clocked

DCDC_IN

26.5

41.8

A

VDD_LPSR_IN

38.2

46.9

VDD_SNVS_IN

3.9

11.3

A

Total

126.160

154.945

Set Point

#12 Active

• CM7 is power off; CM4 runs at 100 MHz, lower

voltage to 0.9 V

• CM4 domain bus frequency at 50 MHz

• Enables ECC for CM4 TCM and OCRAM

• DCDC is off, LDO_LPSR_ANA and

LDO_LPSR_DIG are active

• 16 MHz, 400 MHz, and external 32 kHz crystal

are enabled

• All PLLs are power gated

• The WAKEUPMIX domain, MEGAMIX domain,

and DISPLAYMIX domain are power gated

• All peripherals in LPSRMIX domain are clocked

DCDC_IN

26.2

41.1

A

VDD_LPSR_IN

22.9

28.9

VDD_SNVS_IN

3.9

A

Total

75.669

95.542

Set Point #0

Standby

Suspend

• System is on STANDBY mode

• Both CM7 and CM4 are on SUSPEND mode

• TCM with ECC is on retention

• LDO_LPSR_ANA and LDO_LPSR_DIG are

bypassed

• All clock sources are turned off except for 32 kHz

RTC

• All PLLs are power gated

• All peripherals are clock gated, but remain

powered

DCDC_IN

19.4

VDD_LPSR_IN

29.9

41.1

A

VDD_SNVS_IN

3.9

10.8

A

Total

10.012

64.191

Table 13. Typical power modes current and power consumption (Dual core) (continued)

PIMXRT516SCVP5A Datasheet(PDF) 30 Page - NXP Semiconductors

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