PIMXRT516SCVP5A datasheet(33/124 Pages) NXP

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Electrical characteristics

i.MX RT1160 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 04/2021

NXP Semiconductors

•

Irreversible damage to the processor (worst-case scenario)

Figure 4 shows the power sequence.

Figure 4. Power sequence

4.2.1.1

Power-up sequence

The below restrictions must be followed:

•

VDD_SNVS_IN supply must be turned on before any other power supply or be connected

(shorted) with VDD_LPSR_IN and DCDC_IN supply.

•

If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other

supply is switched on.

•

When internal DCDC is enabled, external delay circuit is required to delay the

“DCDC_PSWITCH” signal at least 1 ms after DCDC_IN is stable.

•

Need to ensure DCDC_IN ramps to 3.0 V within 0.2 x RC, RC is from external delay circuit used

for DCDC_PSWITCH and must be longer than 1 ms.

•

POR_B (if used) must be held low during the entire power up sequence.

NOTE

The POR_B input (if used) must be immediately asserted at power-up and

remain asserted until after the last power rail reaches its working voltage. In

the absence of an external reset feeding the POR_B input, the internal POR

module takes control. See the i.MX RT1160 Reference Manual

(IMXRT1160RM) for further details and to ensure that all necessary

requirements are being met.

VDD_SNVS_IN

VDD_SNVS_ANA

VDD_SNVS_DIG

VDD_LPSR_IN

VDD_LPSR_ANA

VDD_LPSR_DIG

DCDC_IN

VDDA_1P8

VDD_SOC_IN

1ms

DCDC_PSWITCH

POR_B

ONOFF

PIMXRT516SCVP5A Datasheet(PDF) 33 Page - NXP Semiconductors

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