PIMXRT516SCVP5A datasheet(94/124 Pages) NXP

94 / 124 page

i.MX RT1160 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 04/2021

NXP Semiconductors

Electrical characteristics

Figure 48. RMII mode signal timing diagram

4.9.4.3

RGMII signal switching specifications

The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver

devices.

Table 93. RMII signal timing

Characteristic

Min.

Max.

Unit

M16

ENET_CLK pulse width high

35%

65%

ENET_CLK period

M17

ENET_CLK pulse width low

35%

65%

ENET_CLK period

M18

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid

—

M19

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid

—

M20

ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER

to ENET_CLK setup

2—

M21

ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER

hold

2—

Table 94. RGMII signal switching specifications1

Symbol

Description

Min.

Max.

Unit

Tcyc

Clock cycle duration

7.2

8.8

TskewT

Data to clock output skew at transmitter

-500

500

ENET_CLK (input)

ENET_TX_EN

M16

M17

M18

M19

M20

M21

ENET_RX_DATA[1:0]

ENET_TX_DATA (output)

ENET_RX_ER

ENET_RX_EN (input)

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