Table 8-6. OECR1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

OUT_EN_CLK5

R/W

1h

This bit controls the output enable signal for output channel CK5_P/

CK5_N.

0h = Output Disabled

1h = Output Enabled

6

OUT_EN_CLK4

R/W

1h

This bit controls the output enable signal for output channel CK4_P/

CK4_N.

0h = Output Disabled

1h = Output Enabled

5

OUT_EN_CLK3

R/W

1h

This bit controls the output enable signal for output channel CK3_P/

CK3_N.

0h = Output Disabled

1h = Output Enabled

4

OUT_EN_CLK2

R/W

1h

This bit controls the output enable signal for output channel CK2_P/

CK2_N.

0h = Output Disabled

1h = Output Enabled

3

Reserved

R/W

1h

Reserved

2

OUT_EN_CLK1

R/W

1h

This bit controls the output enable signal for output channel CK1_P/

CK1_N.

0h = Output Disabled

1h = Output Enabled

1

OUT_EN_CLK0

R/W

1h

This bit controls the output enable signal for output channel CK0_P/

CK0_N.

0h = Output Disabled

1h = Output Enabled

0

Reserved

R/W

1h

Reserved

8.6.1.3 OECR2 Register (Address = 2h) [reset = 0Fh]

OECR2 is shown in OECR2 Register Field Descriptions.

Return to the Summary Table.

The OECR2 register contains bits that enable or disable individual output clock channels [7:6].

Table 8-7. OECR2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-3

Reserved

R/W

1h

Reserved

2

OUT_EN_CLK7

R/W

1h

This bit controls the output enable signal for output channel CK7_P/

CK7_N.

0h = Output Disabled

1h = Output Enabled

1

Reserved

R/W

1h

Reserved

0

OUT_EN_CLK6

R/W

1h

This bit controls the output enable signal for output channel CK6_P/

CK6_N.

0h = Output Disabled

1h = Output Enabled

8.6.1.4 OERDBK Register (Address = 3h) [reset = 0h]

OERDBK is shown in Table 8-8.

Return to the Summary Table.

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CDCDB800

SNAS818 – JULY 2021

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