8.6.1.8 BTRDCNT Register (Address = 7h) [reset = X]

BTRDCNT is shown in Table 8-12.

Return to the Summary Table.

The BTRDCNT register contains bits [4:0] which configure the number of bytes which will be read back.

Table 8-12. BTRDCNT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R

0h

Reserved

4-0

BYTE_COUNTER

R/W

8h

Writing to this register configures how many bytes will be read back.

8.6.1.9 OUTSET Register (Address = 8h) [reset = X]

OUTSET is shown in Table 8-13.

Return to the Summary Table.

Bit5 of the OUTSET register sets the termination for all the outputs while bit4 can be used to set the power-down

state for all outputs. The remaining bits for this register are reserved.

Table 8-13. OUTSET Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

R

0h

Reserved

5

CH_ZOUT_SEL

R/W

0h

Select between 85 Ω (0) and 100 Ω (1) Output impedance

4

d_DRIVE_OP_STATE_CTRL

R/W

0h

Power-down state of all output clocks.

0: LOW/LOW

1: TRI_STATE

3-0

Reserved

R

0h

Reserved

8.6.1.10 CAPTRIM Register (Address = 76h) [reset = X]

CAPTRIM is shown in Table 8-15.

Return to the Summary Table.

Bits [7:4] of the CAPTRIM register is used to control the slew rate for output channel cluster 2. Bits [3:0] control

the slew rate for output channel cluster 1. Refer below for cluster identification.

Table 8-14. Cluster Identification

Cluster

Outputs

1

CK3, CK2, CK1, CK0

2

CK7, CK6, CK5, CK4

Table 8-15. Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CLUSTER2_CAP_TRIM

R/W

Ch

Slew Rate Reduction Cap Trim for Cluster 2. Default value of Ch.

0: minimum

F: maximum

3-0

CLUSTER1_CAP_TRIM

R/W

Ch

Slew Rate Reduction Cap Trim for Cluster 1. Default value of Ch.

0: minimum

F: maximum

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CDCDB800

SNAS818 – JULY 2021

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