MAX9850 Evaluation System/Evaluation Kit

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Figure 6. Master (Non-Integer) Mode

Figure 7. Master (Integer) Mode

Provided Clock selection. Depending on the desired

mode of operation (see the

MAX9850 Mode Setup sec-

tion) digital audio data can be synchronized to the

master clock signal. The on-board S/PDIF receiver per-

forms the synchronization of the digital audio data to

the chosen MAX9850 master clock signal. To synchro-

nize the digital audio to the MAX9850 master clock,

check the Synchronize Data with Clock checkbox.

Note: When using the Recovered Master Clock as the

master clock frequency, the digital audio data will

always be synchronized.

The MAX9850 uses a frequency-divided master clock

signal throughout the IC (see the

MAX9850 Mode

Setup section). Select the desired internal clock-divider

ratio from the Internal Clock Divide Ratio pulldown.

The MAX9850 EV kit software is capable of calculating

the master clock, internal clock, and charge-pump

clock frequencies. Press the Update Clocks in Status

Bar button to display the calculated values. Checking

the Automatically Update Clocks checkbox will

update the calculated values on a regular basis.

MAX9850 Mode Setup

The MAX9850 Mode Setup window alters its appear-

ance depending on which mode is selected. Figures

6–9 show the different appearances of these windows.

Both Master (Non-Integer) and Master (Integer)

modes of the MAX9850 EV kit software (Figures 6 and

7) are similar in operation. Select Manual Control to

write directly to the MAX9850 registers. Enter the num-

ber in the MSB/LSB edit box in Master (Non-Integer)

and LSB in Master (Integer) mode and press the

Update button to write to the MAX9850. Alternatively,

the Automatic mode can be selected and a desired

Figure 8. Slave (Non-Integer) Mode