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IMX6SDLCEC Datasheet(PDF) 54 Page - NXP Semiconductors |
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IMX6SDLCEC Datasheet(HTML) 54 Page - NXP Semiconductors |
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54 / 169 page ![]() i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 54 NXP Semiconductors Electrical Characteristics 4.9.3.2 General EIM Timing-Synchronous Mode Figure 13, Figure 14, and Table 42 specify the timings related to the EIM module. All EIM output control signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge according to corresponding assertion/negation control fields. , Figure 13. EIM Outputs Timing Diagram Figure 14. EIM Inputs Timing Diagram WE4 EIM_ADDRxx EIM_CSx_B EIM_WE_B EIM_OE_B EIM_BCLK EIM_EBx_B EIM_LBA_B Output Data ... WE5 WE6 WE7 WE8 WE9 WE10 WE11 WE12 WE13 WE14 WE15 WE16 WE17 WE3 WE2 WE1 Input Data EIM_WAIT_B EIM_BCLK WE19 WE18 WE21 WE20 |
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