IMX7ULPIECB2 datasheet(48/112 Pages) NXP

48 / 112 page

PLL VCO (MHz)

FRAC (N)

PFD Output (MHz)

528

792

528

731.07

528

678.8

528

633.6

528

594

528

559.0588235

528

500.2105263

528

475.2

528

452.5714286

528

432

528

413.217

528

396

528

380.16

528

365.538

528

352

528

339.428

528

327.724

528

316.8

528

306.580

528

297

528

288

528

279.529

528

271.5

7.2.5 Audio tunable clock

For audio applications where the data stream is coming from a remote source, the

device has to locally tune a clock signal to match the remote system clock. The

Auxiliary PLL, which provides the clock for master audio, has synchronization logic to

support on-the-fly configuration changes. This allows the device to generate a tunable

clock for audio stream. The clock from one of the Auxiliary PLLs (PLL1) can be

divided by the post-dividers in analog and also the dividers in SCG module. The

divided tunable clock generated should meet the following requirement:

• Output center frequency of 12.288 MHz or 11.2896 MHz

• Tunable range of ± 1000 ppm

• Tunable resolution of 1 ppm

System specifications

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

IMX7ULPIECB2 Datasheet(PDF) 48 Page - NXP Semiconductors

IMX7ULPIECB2 Datasheet(HTML) 48 Page - NXP Semiconductors

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