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IMX7ULPIECB2 Datasheet(PDF) 94 Page - NXP Semiconductors

Part # IMX7ULPIECB2
Description  i.MX 7ULP Applications Processor-Industrial
PDF  112 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

IMX7ULPIECB2 Datasheet(HTML) 94 Page - NXP Semiconductors

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Table 59. I2S/SAI slave mode timing (continued)
Num.
Parameter
Min
Max
Unit
S13
I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/
I2S_RX_BCLK
13
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/
I2S_RX_BCLK
1
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
22.8
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
1
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
12
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
1
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid1
—
17.0
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S15
S13
S15
S17
S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input)
S19
Figure 36. I2S/SAI timing — slave modes
9.2.4.5 VLPR, VLPW, and VLPS mode performance
This section provides the operating performance for the device in VLPR, VLPW, and
VLPS modes.
Table 60. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
Num.
Parameter
Min
Max
Unit
S1
I2S_MCLK cycle time
60
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
100
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/I2S_RX_FS
output valid
—
15
ns
Table continues on the next page...
Specifications—real-time domain
94
i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021
NXP Semiconductors



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