Z86D7308HSC datasheet(63/92 Pages) ZILOG

63 / 92 page

Z86D73

40/44/48-Pin Low-Voltage IR OTP

PS019402-1103

Power-On Reset (POR)

A timer circuit clocked by a dedicated on-board RC oscillator is used for the

Power-On Reset (POR) timer function. The POR time allows VCC and the oscilla-

tor circuit to stabilize before instruction execution begins.

The POR timer circuit is a one-shot timer triggered by one of three conditions:

•

Power Fail to Power OK status, including Waking up from VBO Standby

• Stop-Mode Recovery (if D5 of SMR = 1)

• WDT Timeout

The POR timer is a nominal 5 ms. Bit 5 of the Stop-Mode Register determines

whether the POR timer is bypassed after Stop-Mode Recovery (typical for external

clock, RC and LC oscillators).

HALT

HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/

timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain

active. The devices are recovered by interrupts, either externally or internally gen-

erated. An interrupt request must be executed (enabled) to exit HALT Mode. After

the interrupt service routine, the program continues from the instruction after the

HALT.

STOP

This instruction turns off the internal clock and external crystal oscillation, thereby

reducing the standby current to 10

µA or less. STOP Mode is terminated only by a

reset, such as WDT timeout, POR, SMR, or external reset. This condition causes

the processor to restart the application program at address 000Ch. In order to

enter STOP (or HALT) mode, first flush the instruction pipeline to avoid suspend-

ing execution in mid-instruction. Execute a NOP (Op Code = FFh) immediately

before the appropriate sleep instruction, as follows:

NOP

; clear the pipeline

STOP

; enter STOP Mode

NOP

; clear the pipeline

HALT

; enter HALT Mode

Z86D7308HSC Datasheet(PDF) 63 Page - Zilog, Inc.