Z86D7308HSC datasheet(39/92 Pages) ZILOG

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Z86D73

40/44/48-Pin Low-Voltage IR OTP

PS019402-1103

LVD(D)0Ch Low-Voltage Detection Register

The LVD flag will be valid after enabling the detection for 20

µS (design

estimation, not tested in production). LVD does not work at STOP mode. It

must be disabled during STOP mode in order to reduce current.

Do not modify register P01M while checking a low-voltage condition.

Switching noise of both ports 0 and 1 together might trigger the LVD flag.

HI8(D)0Bh

This register holds the captured data from the output of the 8-bit Counter/Timer0.

Typically, this register is used to hold the number of counts when the input signal

is 1.

L08(D)0Ah

This register holds the captured data from the output of the 8-bit Counter/Timer0.

Typically, this register is used to hold the number of counts when the input signal

is 0.

Field

Bit Position

Description

LVD

765432--

Reserved

No Effect

------1-

LV flag set

LV flag reset

-------0

R/W

Enable LVD

Disable LVD

*Default after POR

Field

Bit Position

Description

T8_Capture_HI

76543210

Captured Data

No Effect

Field

Bit Position

Description

T8_Capture_L0

76543210

Captured Data

No Effect

Note:

Z86D7308HSC Datasheet(PDF) 39 Page - Zilog, Inc.

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