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ADE9153A Datasheet(PDF) 41 Page - Analog Devices |
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ADE9153A Datasheet(HTML) 41 Page - Analog Devices |
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41 / 50 page ![]() Data Sheet ADE9153A Rev. 0 | Page 41 of 50 Addr. Name Bits Bit Name Settings Description Reset Access 19 ZXAI Set this bit to enable an interrupt when a zero crossing is detected on Current Channel A. 0x0 R/W 18 Reserved Reserved. 0x0 R 17 ZXAV Set this bit to enable an interrupt when a zero crossing is detected on the voltage channel. 0x0 R/W 16 Reserved Reserved. 0x0 R 15 FVARNL Set this bit to enable an interrupt when fundamental reactive energy enters or exits the no load condition. 0x0 R/W 14 VANL Set this bit to enable an interrupt when total apparent energy enters or exits the no load condition. 0x0 R/W 13 WATTNL Set this bit to enable an interrupt when the total active energy enters or exits the no load condition. 0x0 R/W 12 TEMP_RDY Set this bit to enable an interrupt when there is a new temperature reading ready from the temperature sensor. 0x0 R/W 11 RMS_OC_RDY Set this bit to enable an interrupt when the RMS_OC values update. 0x0 R/W 10 PWRRDY Set this bit to enable an interrupt when the power value in the AWATT_ACC, AVA_ACC, and AFVAR_ACC registers update after PWR_TIME 4 kSPS samples. 0x0 R/W 9 DREADY Set this bit to enable an interrupt when new waveform samples are ready. 0x0 R/W 8 EGYRDY Set this bit to enable an interrupt when the power values in the AWATTHR, AVAHR, and AFVARHR registers update, after EGY_TIME 4 kSPS samples or line cycles, depending on the EGY_TMR_MODE bit in the EP_CFG register. 0x0 R/W 7 CF2 Set this bit to enable and interrupt when the CF2 pulse is issued, when the CF2 pin goes from a high to low state. 0x0 R/W 6 CF1 Set this bit to enable and interrupt when the CF1 pulse is issued, when the CF1 pin goes from a high to low state. 0x0 R/W 5 REVPCF2 Set this bit to enabled an interrupt when the CF2 polarity changed sign. 0x0 R/W |
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