56F8335 datasheet(7/160 Pages) FREESCALE

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Device Description

56F8335 Technical Data, Rev. 1

Freescale Semiconductor

Preliminary

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49 General Purpose I/O (GPIO) pins; 28 pins dedicated to GPIO

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External reset input pin for hardware reset

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External reset output pin for system reset

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Integrated low-voltage interrupt module

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JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time

debugging

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Software-programmable, Phase Lock Loop-based frequency synthesizer for the core clock

1.1.5

Energy Information

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Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

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On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled

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On-chip regulators for digital and analog circuitry to lower cost and reduce noise

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Wait and Stop modes available

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ADC smart power management

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Each peripheral can be individually disabled to save power

1.2 Device Description

The 56F8335 and 56F8135 are members of the 56800E core-based family of controllers. Each combines,

on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a

microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because

of their low cost, configuration flexibility, and compact program code, the 56F8335 and 56F8135 are

well-suited for many applications. The devices include many peripherals that are especially useful for

motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and

control, automotive control (56F8335 only), engine management, noise suppression, remote utility

metering, industrial control for power, lighting, and automation applications.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and

optimized instruction set allow straightforward generation of efficient, compact DSP and control code.

The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized

control applications.

The 56F8335 and 56F8135 support program execution from internal memories. Two data operands can be

accessed from the on-chip data RAM per instruction cycle. These devices also provide two external

dedicated interrupt lines and up to 49 General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

1.2.1

56F8335 Features

The 56F8335 includes 64KB of Program Flash and 8KB of Data Flash (each programmable through the

JTAG port) with 4KB of Program RAM and 8KB of Data RAM. A total of 8KB of Boot Flash is

incorporated for easy customer inclusion of field-programmable software routines that can be used to

program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be

56F8335 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc

56F8335 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc

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