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EDB8164B4PR-1DITF-R Datasheet(PDF) 88 Page - Micron Technology |
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EDB8164B4PR-1DITF-R Datasheet(HTML) 88 Page - Micron Technology |
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88 / 152 page ![]() Figure 60: READ with Auto Precharge to Power-Down Entry CK_c CKE1, 2 T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9 CMD DQ DQS_c READ w/AP PRE4 D OUT DOUT DOUT DOUT RL tISCKE BL/23 READ w/AP PRE4 BL/23 CKE1, 2 T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9 CMD DQ D OUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT RL tISCKE BL = 4 BL = 8 CK_t DQS_t CK_c DQS_c CK_t DQS_t Notes: 1. CKE must be held HIGH until the end of the burst operation. 2. CKE can be registered LOW at (RL + RU(tDQSCK/tCK)+ BL/2 + 1) clock cycles after the clock on which the READ command is registered. 3. BL/2 with tRTP = 7.5ns and tRAS (MIN) is satisfied. 4. Start internal PRECHARGE. 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Power-Down 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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