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REF2030-Q1 Datasheet(PDF) 27 Page - Texas Instruments |
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REF2030-Q1 Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 34 page ![]() 12 Layout 12.1 Layout Guidelines Figure 12-1 shows an example of a PCB layout for a data acquisition system using the REF2030-Q1. Some key considerations are: • Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF, and VBIAS of the REF2030-Q1. • Decouple other active devices in the system per the device specifications. • Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring. • Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise pickup. • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary. 12.2 Layout Example C C C V REF V IN REF DIG1 Microcontroller A/D Input Via to GND Plane Via to Input Power Analog Inputs V BIAS GND EN REF1 IN+ VS NC REF2 IN- AIN C GND OUT C C Figure 12-1. Layout Example www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: REF20-Q1 |
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