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STM32WB55 Datasheet(PDF) 129 Page - STMicroelectronics

Part # STM32WB55
Description  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 and 802.15.4 radio solution
PDF  193 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WB55 Datasheet(HTML) 129 Page - STMicroelectronics

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DS11929 Rev 11
129/193
STM32WB55xx STM32WB35xx
Electrical characteristics
169
6.3.12
PLL characteristics
The parameters given in Table 64 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 24: General operating conditions.
Table 63. LSI2 oscillator characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fLSI2
LSI2 frequency
VDD = 3.0 V, TA = 30 °C
21.6
-
44.2
kHz
VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 21.2
-
44.4
tSU(LSI2)(2) LSI2 oscillator start-up time
-
0.7
-
3.5
ms
IDD(LSI2)(2)
LSI2 oscillator power
consumption
-
-
500 1180
nA
1. Guaranteed by characterization results.
2. Guaranteed by design.
Table 64. PLL, PLLSAI1 characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLL_IN
PLL input clock(2)
-2.66
-
16
MHz
PLL input clock duty cycle
-
45
-
55
%
fPLL_P_OUT PLL multiplier output clock P
Voltage scaling Range 1
2
-
64
MHz
Voltage scaling Range 2
2
-
16
fPLL_Q_OUT PLL multiplier output clock Q
Voltage scaling Range 1
8
-
64
Voltage scaling Range 2
8
-
16
fPLL_R_OUT PLL multiplier output clock R
Voltage scaling Range 1
8
-
64
Voltage scaling Range 2
8
-
16
fVCO_OUT PLL VCO output
Voltage scaling Range 1
96
-
344
Voltage scaling Range 2
64
-
128
tLOCK
PLL lock time
-
-
15
40
μs
Jitter
RMS cycle-to-cycle jitter
System clock 64 MHz
-40
-
ps
RMS period jitter
-
30
-
IDD(PLL)
PLL power consumption
on VDD(1)
VCO freq = 96 MHz
-
200
260
μA
VCO freq = 192 MHz
-
300
380
VCO freq = 344 MHz
-
520
650
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the two PLLs.



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