STM32WB55 datasheet(192/193 Pages) STMICROELECTRONICS

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Revision history

STM32WB55xx STM32WB35xx

192/193

DS11929 Rev 11

02-Jul-2020

Added STM32WB35xx devices.

Updated Section 2: Description, Section 3.3.4: Embedded SRAM and

Section 8: Ordering information.

Updated Table 1: Device summary, Table 2: STM32WB55xx and

STM32WB35xx devices features and peripheral counts, Table 7:

Features over all modes and Table 106: Package thermal characteristics.

Added Table 17: STM32WB35xx pin and ball definitions and Table 19:

Alternate functions (STM32WB35xx).

Added Figure 2: STM32WB35xx block diagram, Figure 8:

STM32WB35xx - Power supply overview and Figure 50: STM32WB35xx

UFQFPN48 marking example (package top view),

Updated Figure 1: STM32WB55xx block diagram, Figure 4: External

components for the RF part, Figure 16: Power supply scheme (all

packages except UFBGA129 and WLCSP100), Figure 17: Power supply

scheme (UFBGA129 and WLCSP100 packages) and added footnote to

Figure 9: Clock tree.

Added footnote 1 to Table 8: STM32WB55xx and STM32WB35xx modes

overview.

23-Nov-2020

Updated Features, Section 3.15: Voltage reference buffer (VREFBUF)

and Section 3.28.2: Embedded Trace Macrocell™.

Updated Table 9: STM32WB55xx and STM32WB35xx CPU1 peripherals

interconnect matrix, Table 17: STM32WB35xx pin and ball definitions,

Table 26: RF transmitter BLE characteristics (1 Mbps), Table 27: RF

transmitter BLE characteristics (2 Mbps), Table 31: RF transmitter

802.15.4 characteristics, Table 50: Peripheral current consumption,

Table 54: HSE crystal requirements, Table 55: HSE clock source

requirements, footnote 2 of Table 57: Low-speed external user clock

characteristics and Table 86: VBAT monitoring characteristics.

Added footnote 2 to Table 24, footnote 2 to Table 26 and footnote 2 to

Table 27.

Updated Figure 9: Clock tree and Figure 13: STM32WB55Vx UFBGA129

ballout(1).

Minor text edits across the whole document.

07-Apr-2021

Updated document title, Features, Section 1: Introduction, Section 2:

Description, Section 3.3.4: Embedded SRAM, Section 3.6: RF

subsystem, Section 3.6.2: BLE general description and Section 6.1.2:

Typical values, Section 6.3.10: External clock source characteristics.

Updated Table 2: STM32WB55xx and STM32WB35xx devices features

and peripheral counts, Table 16: STM32WB55xx pin and ball definitions,

Table 17: STM32WB35xx pin and ball definitions, Table 18: Alternate

functions (STM32WB55xx), Table 19: Alternate functions

(STM32WB35xx), Table 23: Main performance at VDD = 3.3 V, Table 50:

Peripheral current consumption, Table 53: Wakeup time using

USART/LPUART and Table 55: HSE clock source requirements.

Updated Figure 3: STM32WB55xx and STM32WB35xx RF front-end

block diagram, Figure 9: Clock tree, Figure 16: Power supply scheme (all

packages except UFBGA129 and WLCSP100), Figure 17: Power supply

scheme (UFBGA129 and WLCSP100 packages) and Figure 29: ADC

accuracy characteristics.

Removed former footnote 3 from Table 83: VREFBUF characteristics.

Table 107. Document revision history (continued)

Date

Revision

Changes

STM32WB55 Datasheet(PDF) 192 Page - STMicroelectronics

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