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STA369BWS Datasheet(PDF) 68 Page - STMicroelectronics |
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STA369BWS Datasheet(HTML) 68 Page - STMicroelectronics |
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68 / 92 page  Register description STA369BWS 68/92 DocID016861 Rev 7 7.12 EQ coefficients and DRC configuration register (addr 0x31) EQ RAM DRC / Anti clipping Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in Table 75 below. Anticlipping when AMGC[3:2] = 01 AC0, AC1, AC2 settings are designed for the loudspeaker protection function, limiting at the minimum any audio artefacts introduced by typical anti-clipping / DRC algorithms. More detailed information is available in the applications notes “Configurable output power rate using STA335BW” and “STA335BWS vs STA335BW”. XOB This bit can be used to bypass the crossover filters. Logic 1 means that the function is not active. In this case, high pass crossover filter works as a pass-through on the data path (b0 = 1, all the other coefficients at logic 0) while the low-pass filter is configured to have zero signal on channel-3 data processing (all the coefficients are at logic 0). D7 D6 D5 D4 D3 D2 D1 D0 XOB Reserved Reserved AMGC[3] AMGC[2] Reserved SEL[1] SEL[0] 00000000 Table 74. EQ RAM select SEL[1:0] EQ RAM bank selected 00 / 11 Bank 0 activated 01 Bank 1 activated 10 Bank 2 activated Table 75. Anti clipping and DRC preset AMGC[3:2] Anti clipping and DRC preset selected 00 DRC / Anti-clipping behavior is described in Table 54 on page 49 (default) 01 DRC / Anti-clipping behavior is described Table 76 on page 68 10 / 11 Reserved Table 76. Anti-clipping selection for AMGC[3:2] = 01 AMGC[1:0] Mode 00 AC0, stereo anticlipping 0dB limiter 01 AC1, stereo anticlipping +1.25 dB limiter 10 AC2, stereo anticlipping +2 dB limiter 11 Reserved do not use |
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