STA369BWS datasheet(81/92 Pages) STMICROELECTRONICS

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STA369BWS

Power down delay selector (PNDLSL[2:0]) bits

As per register MISC1 (addr 0x4B) on page 78, the assertion of PWDN activates a counter

that, by default, after 13 million clock cycles, puts the power bridge in tristate mode

independently from the fade out time. Using these registers it is possible to program this

counter as per the table below.

Short-circuit check enable (SHEN) bit

This bit, when enabled, activates the short-circuit checks before any power bridge activation

(EAPD bit 0 -> 1). See Section 7.17 on page 75 for more details.

7.21

Global DRC after B2DRC (GDRC) bit (addr 0x4D, bit D0)

GDRC bit, when set, changes the architecture configuration of the dual band DRC. As a

consequence, the block diagram, illustrated by the Figure 20: B2DRC scheme on page 69,

becomes that shown in Figure 27 below.

Figure 27. Global DRC after B2DRC

The final effect is a global DRC after the dual band DRC. This architecture aims to limit the

signal overshoot, generated by the different phases of the two processed data paths of the

B2DRC architecture, that could happen between the two bands.

Note:

If GDRC is enabled, C3VR[0] and C3VR[1] must be set to 0 (default values).

Table 90. PNDLSL bits configuration

PNDLSL[2]

PNDLSL[1]

PNDLSL[0]

Fade-out time

Default time (13 x 106 PLL clock cycles)

Default time divided by 2

Default time divided by 4

Default time divided by 8

Default time divided by 16

Default time divided by 32

Default time divided by 64

Default time divided by 128

STA369BWS Datasheet(PDF) 81 Page - STMicroelectronics