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STA369BWS Datasheet(PDF) 87 Page - STMicroelectronics |
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STA369BWS Datasheet(HTML) 87 Page - STMicroelectronics |
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87 / 92 page  DocID016861 Rev 7 87/92 STA369BWS Applications 92 8.2 PLL filter circuit It is recommended to use the above circuit and values for the PLL loop filter to achieve the best performance from the device in general applications. Note that the ground of this filter circuit has to be connected to the ground of the PLL without any resistive path. Concerning the component values, it must be taken into account that the greater the filter bandwidth, the less is the lock time but the higher is the PLL output jitter. 8.3 Typical output configuration Figure 30 shows the typical output configuration used for BTL stereo mode. Please contact STMicroelectronics for other recommended output configurations. Figure 30. Output configuration for stereo BTL mode (RL = 8 |
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