LM5145 datasheet(23/69 Pages) TI

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(nF)

35 t

(ms)

(4)

where

• tSS is the required soft-start time.

SS can be pulled low with an external circuit to stop switching, but this is not recommended. When the controller

is in FPWM mode (set by connecting DEMB to VDDA), pulling SS low results in COMP being pulled down

internally as well. LO remains on and the low-side MOSFET discharges the output capacitor, resulting in large

negative inductor current. In contrast, the LO gate driver is disabled when the LM25143 internal logic pulls SS

low due to a fault condition.

9.3.10 Output Voltage Setpoint (FB1, FB2)

The LM25143 outputs can be independently configured for one of the two fixed output voltages with no external

feedback resistors, or adjusted to the desired voltage using an external resistor divider. VOUT1 or VOUT2 can be

configured as a 3.3-V output by connecting the corresponding FB pin to VDDA, or a 5-V output by connecting

FB to AGND. The FB1 and FB2 connections (either VDDA or GND) are detected during power up. The

configuration settings are latched and cannot be changed until the LM25143 is powered down with the VCC

voltage decreasing below its falling UVLO threshold, and then powered up again.

Alternatively, the output voltage can be set using external resistive dividers from the output to the relevant

FB pin. The output voltage adjustment range is between 0.6 V and 36 V. The regulation threshold at FB is

0.6 V (VREF). Use Equation 5 to calculate the upper and lower feedback resistors, designated RFB1 and RFB2,

respectively. See Figure 9-3.

OUT

FB1

FB2

REF

(5)

The recommended starting value for RFB2 is between 10 kΩ and 20 kΩ.

VOUT1

COMP1

FB1

VREF

gm = 1200 S

RFB1

RFB2

VIN

RCOMP

CCOMP

CHF

–

AGND

Figure 9-3. Control Loop Error Amplifier

The Thevenin equivalent impedance of the resistive divider connected to the FB pin must be greater than 5 kΩ

for the LM25143 to detect the divider and set the channel to the adjustable output mode.

FB1

FB2

FB1

FB2

5 k

(6)

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