DDA002C

http://onsemi.com

6

Electrical Characteristics

Symbol

Rating

Pin

Min

Typ

Max

Unit

SUPPLY SECTION

Turn−on threshold level, Vcc going up

16

11

12

13

V

Minimum operating voltage after turn−on (Note 4)

16

8.5

9.5

10.5

V

Startup voltage on the floating section

19,17

8

9

10

V

Cutoff voltage on the floating section

19,17

7.4

8.4

9.4

V

Istartup

16

−

−

300

mA

Internal IC consumption, no output load on pin 18/17 – 15/14,

Fsw = 300 kHz (Note 5)

16

−

5

−

mA

Internal IC consumption, 1 nF output load on pin 18/17 – 15/14,

Fsw = 300 kHz (Note 5)

16

−

14

−

mA

Internal IC consumption in fault mode

16

−

2.5

−

mA

VOLTAGE CONTROL OSCILLATOR (VCO)

Fsw min

Minimum switching frequency, R_Fmin = 41 kΩ on pin 5,

Vpin 7 > 5.5 V, DT = 300 ns (Notes 19 and 21)

5

58

60

62

kHz

Fsw max

Maximum switching frequency, R_Fmax = 2.5 kΩ on pin 6,

Vpin 7 < 1.2 V, DT = 100 ns, Rt = 41 kΩ (Notes 20 and 21)

6

450

500

550

kHz

SVCO

Maximum VCO conversion slope, Df / ΔVfb (Note 6)

−

−

120

−

kHz / V

FBSW min

Feedback pin swing above which Df = 0, Fsw = Fmin, DC = 50%

7

−

5.1

−

V

FBSW max

Feedback pin swing below which Df = 0, Fsw = Fmax, DC = 50%

(Note 6)

7

−

1.2

−

V

DCsl, DCsh

Operating duty−cycle symetry, 5.5 V> Vpin 7 > 0.5 V (Note 7)

18,17;

15,14

48

50

52

%

Minimum On time

18,17;

15,14

−

880

−

ns

VFB_DC_0

Skip comparator threshold on the feedback pin (Note 8)

7

−

1.2

−

V

VFB_DC_0_

Hyste

Hysteresis on the skip comparator

7

−

50

−

mV

VREF

Reference voltage for Fmin current generation

5

−

2

−

V

FEEDBACK SECTION

Rfb

Internal pull−up resistor

7

−

10

−

kΩ

Vfb_O

Open−loop voltage on the feedback pin, no optocoupler connection

7

−

7.3

−

V

5. Outputs Lgs and Hgs (pin 9/10) are unloaded.

6. Guaranteed by design.

7. DCsh = (DChs/(DChs + DCls)) * 100%, DCsl = (DCls/(DChs + DCls)) * 100%

8. The VFB_DC_0 is the FB voltage below which are all outputs disabled.

The FB voltage has to increases to VFB_DC_0 + VFB_DC_0_Hyste to re−enable all outputs of the controller.

10.Pins 17, 18 and 19 are on the same potencial during IHV_LEAK measurements

11. On−time on synchro outputs wont be longer than on−time on power outputs.

12.The soft start pin is pulled down by an internal switch until the CIG timer ending voltage is reached

13.FB timer is disabled until the soft−start ending voltage is reached

14.EN1 input is blanked until the preheat period (CIG) ends. The OTP input is blanked during full startup sequence made of: PFC_del + CIG_t + SS_t

15.The FB timeout circuit starts to operate at the end of PFC_del + CIG_t + SS_t period.

17.The EN1 and EN2 input voltages have to go 50 mV below VEN1, VEN2 to release these inputs.

18.The OTP input voltage has to go 50 mV above OTPref_V to release this input.

19.The R_Fmin pin do not accept any bypass capacitor

20.Maximum acceptable capacitance connected to the pin is 100 pF