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VV5430 Datasheet(PDF) 25 Page - STMicroelectronics

Part # VV5430
Description  Monochrome Analog Output CMOS Image Sensors
PDF  33 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

VV5430 Datasheet(HTML) 25 Page - STMicroelectronics

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VV5430
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CD5430F-A
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Setup Code_1
Header Code = 0001
Valid data bits: 11
The code_1 setup register is used to select different basic operating modes:
Note: Decreasing the system clock rate proportionately increases sensor sensitivity (by increasing exposure time), but
also decreases frame frequency. System Clock must be x1 for standard CCIR or EIA framing.
Bit
Function
Default
Comment
0
Normal/Backlit
0
Selects between normal and backlit exposure modes. The
power-on default is normal mode. See Exposure Control
for full description
1
Linear Correction enable
0
Selects between a linear (LIN=1) or gamma corrected
video signal on AVO. The power-on default is gamma cor-
rected.
2
Auto gain control enable
1
Allows automatic gain control to be inhibited. The current
gain value selected is frozen. With AGC=0 a new gain
value can be written to the gain register via the serial inter-
face (header code 0101).
3
Inhibit black calibration
0
Allows automatic black calibration to be inhibited.
4
Auto exposure control enable
1
Allows automatic exposure control to be inhibited. The cur-
rent exposure value selected is frozen. Note that if auto-
matic exposure control is inhibited then automatic gain
control is also disabled. With AEC=0 a new exposure
value can be selected by writing to the coarse and fine
exposure registers via the serial interface (header codes
0011 & 0100).
5
Horizontal shuffle enable
0
Shuffles the read out of the horizontal shift register. Even
columns read out together then odd columns.
6
Vertical shuffle enable
0
Shuffles the readout of the vertical shift register. Even
lines read out together then odd lines.
7
Force black calibration
1
Requests a re-calibration of the black level while bit is low.
8
Clock divisor DIV0
0
System clock division: (see Note)
0,0=1; 0,1=÷2; 1,0=÷4; 1,1=÷8
9
Clock divisor DIV1
0
10
Internal Register
0
This bit must be set to 0 for correct sensor operation
11
Not used
0
Table 15 : Set-up code_1



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