FXLS8964AF datasheet(15/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

during a read operation. When applied, clock stretching occurs after the ACK issued by

the I2C bus primary.

A LOW-to-HIGH transition on the SDA line while the SCL line is high is defined as a stop

condition (SP) signal. The primary issuing the SP signal always terminates a write or

burst write. A primary should properly terminate a read by not acknowledging a byte at

the appropriate time in the protocol, followed by the SP signal. A primary may also issue

a repeated start signal (SR) during a transfer.

12.1.2 I2C read/write operations

12.1.2.1 Single-byte read

The primary transmits a start condition (ST) to FXLS8964AF, followed by the secondary

address, with the R/W bit set to '0' for a write, and the FXLS8964AF sends an

acknowledgment. Then the primary transmits the address of the register to read and

the FXLS8964AF sends an acknowledgment. The primary transmits a repeated start

condition (SR), followed by the secondary address with the R/W bit set to '1' for a

read from the previously selected register. The FXLS8964AF then acknowledges and

transmits the data from the requested register. The primary does not acknowledge (NAK)

the transmitted data and then transmits a stop condition to end the data transfer.

12.1.2.2 Multiple-byte read

When performing a multi-byte or burst read, FXLS8964AF automatically increments the

the steps of a single-byte read, multiple bytes of data can be read from sequential

can be read until the primary issues a no acknowledge (NAK), followed by a stop

condition (SP) signaling the end of the transfer.

12.1.2.3 Single-byte write

To start a write command, the primary transmits a start condition (ST) to the

FXLS8964AF, followed by the secondary address with the R/W bit set to '0' for a write,

and the FXLS8964AF sends an acknowledgment. Then the primary transmits the

address of the register to write to, and the FXLS8964AF sends an acknowledgment.

Then the primary transmits the 8-bit data to write to the designated register and the

FXLS8964AF sends an acknowledgment signaling it has received the data. Since this

transmission is complete, the primary transmits a stop condition (SP) to end the data

transfer. The data sent to the FXLS8964AF is now stored in the appropriate register.

12.1.2.4 Multiple-byte write

FXLS8964AF automatically increments the register address write pointer after a write

command is received. Therefore, after following the steps of a single-byte write, multiple

bytes of data can be written to sequential registers after each acknowledgment (ACK) is

received.

FXLS8964AF

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Product data sheet

Rev. 3.4 — 7 December 2021

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