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FXLS8964AF Datasheet(PDF) 19 Page - NXP Semiconductors |
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FXLS8964AF Datasheet(HTML) 19 Page - NXP Semiconductors |
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19 / 98 page  NXP Semiconductors FXLS8964AF 3-Axis Low-g Accelerometer aaa-040843 High-Impedance SPI_MISO SPI_DATA SCLK SPI_CS_B A6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A5 A4 A3 A2 R/W A1 A0 X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 Figure 11. SPI multiple-byte read protocol diagram (3-wire mode) 13.5 SPI timing specifications (4-wire mode and 3-wire hardwired modes) Table 13 and Figure 12 specify and illustrate the minimum and maximum timing parameter values for correct SPI interface functionality when FXLS8964AF is operated in 4-wire and 3-wire hardwired SPI modes. FXLS8964AF only supports SPI mode 00, corresponding to CPOL = 0, and CPHA = 0. In this mode, the active state of the clock is high and the idle state is low. Data is latched on the rising edge of the clock and propagated on the falling edge. All timing specifications shown in Table 13 were determined under the following conditions: 10 pF capacitor and 1 kΩ pull-up resistor present on all SPI signals, 105 °C, 1.8 V. Specifications Label Description Min. Max. Unit fSCLK SCLK frequency 0 4 MHz tSCLK SCLK Period 250 — ns tSCLKH SCLK high time 100 — ns tSCLKL SCLK low time 100 — ns tHZ Hold time for SPI_MISO signal (transition back to high-z state) — 15 ns tSCS Setup time for SPI_CS_B signal 125 — ns tHCS Hold time for SPI_CS_B signal 240 — ns tWCS Inactive time for SPI_CS_B signal 600 — ns tSET Data setup time for SPI_MOSI signal 10 — ns tHOLD Data hold time for SPI_MOSI signal 10 — ns tDDLY Setup time for SPI_MISO signal (transition out of high-z state) — 50 ns Table 13. Secondary timing values FXLS8964AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 3.4 — 7 December 2021 19 / 98 |
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