FXLS8964AF datasheet(51/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

Field

Description

INT2_FUNC

INT2 output / EXT_TRIG input pin selection

0 (default): INT2/EXT_TRIG pin is configured for the INT2 output function. The logic polarity and

output driver type are specified in the

INT_POL and INT_PP_OD registers. Interrupt signals are

selectively routed to this output pin using the

INT_PIN_SEL register.

1: INT2/EXT_TRIG pin is configured as the EXT_TRIG input function. A positive edge (low-to-high)

transition on the EXT_TRIG pin is used to trigger either a single measurement of the acceleration and

temperature data using the current decimation settings when EXT_TRIG_M = 1 or a single acquisition

of the current acceleration and temperature data when EXT_TRIG_M = 0. This function is useful for

realizing low frequency or asynchronous ODRs initiated by the host system, for example, by using an

MCU timer output pin. When this function is enabled, it is reflected in the

SYS_MODE register.

Notes:

• When the EXT_TRIG function is enabled, any bits set to '1' in the INT_PIN_SEL register (mapping

an event flag to the INT2 output pin) are ignored as the pin becomes a dedicated high-impedance

input pin for the external trigger function.

• The INT2_FUNC bit setting is ignored when BT_MODE = VDD as the external trigger function is not

available in this mode.

INT_PP_OD

INT1 and INT2 pins output driver selection

0 (default): INTx output pin driver is push-pull type.

1: INTx output pin driver is open-drain/open-source type. An external pull-up/pull-down resistor is

required.

Notes:

• If a user operation sets INT_PP_OD before issuing a soft reset command, the setting is maintained

through the reset sequence (only lost when VDD supply is removed or Hibernate mode is enabled).

• The INT_PP_OD bit setting is ignored when BT_MODE = VDD as the INT1/MOT_DET and INT2/

BOOT_OUT output driver type is fixed to open-drain.

INT_POL

Interrupt logic polarity on INT1 and INT2 pins

Selects the polarity of the interrupt output signal on the INT1 and INT2 pins.

0: Active low: interrupt events are signaled with a logical '0' level. If DRDY_PUL=1, a SRC_DRDY

event pulse is negative going. The inactive state of the INTx pins is logic '1' (VDD).

1 (default): Active high: interrupt events are signaled with a logical '1' level. If DRDY_PUL=1, a SRC_

DRDY event pulse is positive going. The inactive state of the INTx pins is logic '0' (GND).

Notes:

• If a user operation sets INT_POL before issuing a soft reset command, the setting is maintained

through the reset sequence (only lost if VDD supply is removed or Hibernate mode is enabled).

• The INT_POL bit setting is ignored when BT_MODE = VDD as the INT1/MOT_DET and INT2/

BOOT_OUT interrupt logic polarity is fixed at active low (external pull-up resistors are required).

Table 56. SENS_CONFIG4 register (address 18h) bit description...continued

[1]

In order to acquire all the measurements specified by the decimation setting, only one trigger event is needed.

INTx pin configuration

INT_PP_OD

INT_POL

INTx pin asserted value

INTx pin

deasserted value

CMOS output

External pull-up resistor added

(open-drain)

High-Z[1]

Table 57. INTx pin behavior as a function of INT_PP_OD and INT_POL bit settings (valid only when BT_MODE =

VDD)

FXLS8964AF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.4 — 7 December 2021

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