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F1385EVS Datasheet(PDF) 1 Page - Renesas Technology Corp

Part # F1385EVS
Description  DPD Demodulator for PA Linearization 3200 to 4400 MHz
PDF  42 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

F1385EVS Datasheet(HTML) 1 Page - Renesas Technology Corp

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DPD Demodulator for PA
Linearization 3200 to 4400 MHz
F1385
Datasheet
© 2022 Renesas Electronics Corporation
1
February 7, 2022
Description
This document describes the specification for the F1385 Digital
Pre-Distortion Demodulator for PA linearization. This series of
devices is offered in two frequency variants to cover common
UTRA bands.
Competitive Advantage
In typical Base Station transmitters digital pre-distortion is
employed to improve the transmitter performance. The signal out
of the PA is sampled and the incoming TX chain I & Q data is pre-
distorted to counteract the distortion inherent in the PA. The PA
signal is adjusted via a digital step attenuator to a lower level and
then sub-sampled at an IF frequency of ~350 MHz which
necessitates the need for a highly linear demodulator to
downconvert to quadrature IF from the transmit frequency. By
sampling IF_I and IF_Q independently and then digitally
combining these signals, an effective doubling of the sample rate
can be achieved. Any distortion in this path will degrade the
performance of the DPD algorithm. By utilizing an ultra-linear
demodulator with integrated DSA such as the F1385, the ACLR
and/or power consumption of the full TX system can be improved
significantly.
DPD full path ACLR: Reduced by 1 dB
Icc: Typically 45% less current
Zero-DistortionTM eliminates 2 IF amps
Integrates 2 Baluns, SP2T RF switch
Glitch-FreeTM gain control
Features
Wide flat performance IF BW
Wide RF BW (~ 1.2 GHz)
Ideal for Multi-Carrier Systems
Drives ADC directly
Ultra linear +39 dBm OIP3
Excellent ACLR performance
100 Ω differential output impedance
Fully integrated DPD demodulator
6 x 6 mm 36-pin package
Standby Mode w/Fast Recovery
ICC: 210 mA
Block Diagram
Figure 1. Block Diagram
90
O
.
LO
SPI
DEC
Bias
Ctrl
STBY
ISET
IBIAS
CLK
DATA
CSb
2
IFI
IFQ
RFY
RFX


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