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F0440 Datasheet(PDF) 5 Page - Renesas Technology Corp |
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F0440 Datasheet(HTML) 5 Page - Renesas Technology Corp |
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5 / 29 page ![]() F0440 Datasheet © 2021 Renesas Electronics Corporation 5 November 4, 2021 Electrical Characteristics Table 5. Electrical Characteristics See F0440 Typical Application Circuit. VCC = +5V, TC = +25°C, Specifications apply operated as a dual-path RF DVGA unless otherwise noted, Max gain setting, output power = 0dBm, ZRFI = ZRFO = 50Ω, unless otherwise noted. Parameter Symbol Condition Minimum Typical Maximum Units Logic Input High VIH These apply for 5V, 3.3V, and 1.8V logic levels 1.1 [a] V Logic Input Low VIL 0.63 Logic Current (per pin) IIH, IIL STBY_A, STBY_B 5V logic -5 127[b] μA 3.3V logic -5 87 1.8V logic -5 47 SPI_, VCTRL0, VCTRL1, VCTRL2 3.3V logic -5 5 1.8V logic -5 5 Supply Current ICC_LB Low Band Configuration 245 mA ICC_MB Mid Band Configuration 245 270 ICC_HB High Band Configuration 245 ICC_STBY Standby Mode[c] 7 14 Startup time Tstart 50% of STBY going low to Gain within ±1dB with no attenuation. 74 ns DSA0 Adjust Range / Step GSTEP0 6 dB DSA1 Adjustment Range GADJ1 23 dB DSA1 Step GSTEP1 1 dB DSA2 Adjustment Range GADJ2 18 dB DSA2 Step GSTEP2 6 dB Max Attenuation Glitch ATTNG 2 dB DSA0 Gain Settling Time [d] ATT0_SW_0to6 50% CTL to within 0.1dB final value, 0 dB state to 6dB state 24 35 ns ATT0_SW_6to1 50% CTL to within 0.1dB final value, 6dB state to 0dB state 18 35 ns DSA2 Gain Settling Time ATT2_SW_0to18 50% CTL to within 0.1dB final value, 0dB state to 18dB state 16 35 ns ATT2_SW_18to0 50% CTL to within 0.1dB final value, 18 dB state to 0dB state 15 35 ns DSA1 Gain Settling Time DSA1ST 50% of CSb to within 0.1dB final value 300 ns DSA2 Phase Settling Time ATT2_PH_0to18 50% CTL to within 1 degree of final value, 0dB state to 18dB state 16 35 ns ATT2_PH_18to0 50% CTL to within 1 degree of final value, 18dB state to 0dB state 15 35 ns Stability K Factor KFACT Over entire temperature range 1.4 unit |
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