F0440 Datasheet

© 2021 Renesas Electronics Corporation

6

November 4, 2021

Parameter

Symbol

Condition

Minimum

Typical

Maximum

Units

Serial Clock Speed

10

MHz

CSb_A, CSb_B to First Serial

Clock Rising Edge

A

SPI 3 wire Bus. 50% of CSb falling

edge to 50% of CLK rising edge.

10

ns

Serial Data Hold Time

B

SPI 3 wire Bus. 50% of CLK rising

edge to 50% of Data falling edge.

10

ns

Final Serial Clock Rising Edge

to CSb

C

SPI 3 wire Bus. 50% of CLK rising

edge to 50% of CSb rising edge.

10

ns

DSA0 Phase Settling Time

value, 0dB state to 6dB state

24

35

ns

value, 6dB state to 0dB state

18

35

ns

a. Items in min/max columns in bold italics are confirmed by Test.

b. Items in min/max columns that are not bold/italics are confirmed by Design Characterization.

c. During standby mode, SPI is to be left ON and previous state shall be maintained when device is powered up.

d. Time for the gain to settle within ±0.1dB and relative to SPI command latch.

Table 6. Electrical Characteristics – 450MHz Performance

de-embedded, unless otherwise noted.

Parameter

Symbol

Condition

Minimum

Typical

Maximum

Units

RF Input Return Loss

11

dB

RF Output Return Loss

14.5

dB

Gain

11

dB

Maximum attenuation

-35

Variation over Temperature

0.7

DSA0 Absolute Error

±0.07

dB

DSA1 Step Error

±0.05

dB

DSA1 Absolute Error

±0.15

dB

DSA2 Step Error

±0.11

dB

DSA2 Absolute Error

±0.25

dB

Relative Phase DSA0

1.7

Deg

Phase Deviation DSA1

0.16

Deg

Relative Phase DSA2

7.7

Deg

Noise Figure

5

dB

5.7

DSA1 22dB attenuation

27.7

Output Third Order Intercept Point

1MHz tone separation

38

dBm