F0440 Datasheet

© 2021 Renesas Electronics Corporation

20

November 4, 2021

Programming

Serial Control Mode

Figure 47. Serial Register Timing Diagram (LSB-FIRST)

Table 13. DSA1 Serial Mode Default Condition

When the device is first powered up, DS1 will default to the Maximum Attenuation setting as shown.

Note – F0440 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device is not being

Data Word

Latched into

Active Register

CLK

1

2

3

4

5

6

7

8

9

CSb

DATA

D1

D0

D2

D6

D3

D5

D4

LSB

X

X

1 dB

2 dB

4 dB

X

8 dB 16 dB

D7

X - don’t care

MSB

Data Word 8 bits

Default Register Setting

x

x

x

1

1

1

1

1

LSB

MSB

D0

D1

D2

D3

D4

D5

D6

D7