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RZ/T2M Datasheet(PDF) 71 Page - Renesas Technology Corp |
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RZ/T2M Datasheet(HTML) 71 Page - Renesas Technology Corp |
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71 / 127 page  CKIO tDACD tDACD Tr Tcw A25 to A0 tAD1 tAD1 tCSD1 tRWD1 A12/A11*1 RD/WR# tCSD1 DACK*2 Trw Tc1 Td1 tRWD1 D31 to D0 tBSD BS# tBSD Row address Column address tAD1 tAD1 tAD1 tAD1 READA command CS3#, CS2# RAS# tRASD1 tRASD1 tCASD1 CAS# tCASD1 DQMUU, DQMUL, DQMLU, DQMLL tDQMD1 tDQMD1 tRDH2 tRDS2 (High) CKE Tde Tap Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.20 Synchronous DRAM single-read bus cycle (with auto precharge, CAS latency 2, WTRCD = 1 cycle, WTRP = 1 cycle) RZ/T2M Datasheet 2. Electrical Characteristics R01DS0383EJ0100 Rev.1.00 Mar 22, 2022 Page 71 of 127 |
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