RZSLASHT2M datasheet(87/127 Pages) RENESAS

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Table 2.24

DMAC timing

Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 12 pF (CKIO), 12 pF (others), Tjmin = -20℃

Parameter

Symbol

Min.*1

Max.

Unit

Reference figure

DMAC

DREQ pulse width

tDRQW

tPLcyc × 2

—

Figure 2.36

DACK and TEND delay time

tDACD

-0.5

Figure 2.37

Note 1. tPLcyc: PCLKL cycle

DREQ

tDRQW

Figure 2.36

DREQ input timing

CKIO

tDACD

DACK

TEND

Figure 2.37

DACK and TEND output timing

2.5.5

On-Chip Peripheral Module Timing

2.5.5.1

I/O Port Timing

Table 2.25

I/O port timing

Parameter

Symbol

Min.

Max.

Unit*1

Reference figure

I/O port

Input data pulse width

tPRW

1.5

—

tPLcyc

Figure 2.38

Note 1. tPLcyc: PCLKL cycle

PCLKL

tPRW

Port

Figure 2.38

I/O port input timing

2.5.5.2

CMTW Timing

Table 2.26

CMTW timing

Parameter

Symbol

Min.

Max.

Unit*1

Reference figure

CMTW

Input capture input pulse

width

Single-edge setting

tCMTWICW

1.5

—

tPLcyc

Figure 2.39

Both-edge setting

2.5

—

Note 1. tPLcyc: PCLKL cycle

RZ/T2M Datasheet

2. Electrical Characteristics

R01DS0383EJ0100 Rev.1.00

Mar 22, 2022

Page 87 of 127

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