RZSLASHT2M datasheet(93/127 Pages) RENESAS

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Table 2.32

SCI timing (1 of 2)

Parameter

Symbol

Min.

Max.

Unit

Reference figure

SCI

(Asynchronous)

Input clock cycle

tScyc

—

tPSCIcyc

Figure 2.55

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rise time

tSCKr

—

Input clock fall time

tSCKf

—

Output clock cycle

tScyc

—

tPSCIcyc

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rise time

tSCKr

—

Output clock fall time

tSCKf

—

SCI

(Simple I2C,

Standard mode)

SDA input rise time

tSr

—

1000

Figure 2.56

SDA input fall time

tSf

—

300

SCL, SDA input spike pulse removal

time

tSP

2 × NFcyc*1

Data input setup time

tSDAS

250

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

—

400

SCI

(Simple I2C,

Fast mode)

SDA input rise time

tSr

—

300

Figure 2.56

SDA input fall time

tSf

—

300

SCL, SDA input spike pulse removal

time

tSP

2 × NFcyc*1

Data input setup time

tSDAS

100

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

—

400

RZ/T2M Datasheet

2. Electrical Characteristics

R01DS0383EJ0100 Rev.1.00

Mar 22, 2022

Page 93 of 127

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