RZSLASHT2M datasheet(94/127 Pages) RENESAS

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Table 2.32

SCI timing (2 of 2)

Parameter

Symbol

Min.

Max.

Unit

Reference figure

SCI

(Clock sync,

Simple SPI)

SCK output clock cycle (master)

tSPcyc

65536

tPSCIcyc

Figure 2.57 to

Figure 2.62

SCK input clock cycle (slave)

65536

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise/fall time

tSPCKR,

tSPCKF

—

Data input setup

time

Internal clock

tSU

—

External clock

—

Data input hold

time

Internal clock

—

External clock

—

Data output delay

time

Internal clock

tOD

—

External clock

—

Data output hold

time

Internal clock

tOH

—

External clock

—

Data rise/fall time

tDR, tDF

—

Slave access time Internal clock

tSA

—

3 × tPSCIcyc + 12

External clock

—

3 × tPSCIcyc + 12

Slave output

release time

Internal clock

tREL

—

3 × tPSCIcyc + 12

External clock

—

3 × tPSCIcyc + 12

SCI

(Simple SPI)

SS input setup time

tLEAD

—

tSPcyc

SS input hold time

tLAG

—

tSPcyc

SS input rise/fall time

tSSR, tSSF

—

Note:

tPSCIcyc: PCLKSCIn cycle

Note 1. NFcyc = 4n × 2m-1 × tPSCIcyc

n: CCR2.CKS[1:0] (n = 0, 1, 2, 3)

m: CCR1.NFCS[2:0] (m = 1, 2, 3, 4)

SCKn

(n = 0 to 5)

tScyc

tSCKW

tSCKf

tSCKr

Figure 2.55

SCK clock input/output timing

RZ/T2M Datasheet

2. Electrical Characteristics

R01DS0383EJ0100 Rev.1.00

Mar 22, 2022

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