RZSLASHT2M datasheet(113/127 Pages) RENESAS

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tMMIIck

ETH2_REFCLK

ETH2_TXDm

ETH2_TXEN

ETH2_TXER

tMMIIs

tMMIIh

ETH2_RXDm

ETH2_RXDV

ETH2_RXER

tMMIId

Figure 2.85

MII transmission and reception timing (MAC to MAC connection mode) (m = 0 to 3)

2.5.5.15

Serial Management Interface Timing

Conditions:

VOH = VCC18 × 0.5, VOL = VCC18 × 0.5, C = 30 pF (1.8 V)

VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 30 pF (3.3 V)

Table 2.40

Serial management interface timing

Parameter

Symbol

Min.

Max.

Unit

Reference figure

MDIO

MDC output cycle time

GMAC_MDC,

ETHSW_MDC

TMDCck

—

Figure 2.86

ESC_MDC

400

—

MDIO output delay time (for MDC fall)*1

TMDIOd

—

MDIO input setup time (for MDC rise)

TMDIOs

—

MDIO input hold time (for MDC rise) GMAC_MDC,

ETHSW_MDC

TMDIOh

—

ESC_MDC

—

Note 1. The output timing from ETHSW is based on the rising edge of MDC, and the output delay can be set in the register.

RZ/T2M Datasheet

2. Electrical Characteristics

R01DS0383EJ0100 Rev.1.00

Mar 22, 2022

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