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RZ/T2M Datasheet(PDF) 119 Page - Renesas Technology Corp |
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RZ/T2M Datasheet(HTML) 119 Page - Renesas Technology Corp |
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119 / 127 page  Table 2.47 Debug interface timing (2 of 2) Parameter Symbol Min. Max. Unit Reference figure Trace clock cycle tTCYC 20 — ns Figure 2.97 Output load: 15 pF Trace data delay time Trace clock: P18_6 tTDT -2.3 3.3 ns Trace clock: P17_4 -2.5 3.0 Trace clock: P22_2 -1.0 4.2 Note 1. This value is the minimum cycle time for the normal operation of internal circuits. The actual cycle time should be determined in consideration of the TCK capture edge timing and cable length of the connected ICE. tTCKcyc tTCKH tTCKL TCK VIH VIH VIL VIL 1/2 VCC33 1/2 VCC33 VIH Figure 2.94 TCK input timing tSWDO tTDOD SWDIO (output) TDO tTMSS tTMSH TMS/SWDIO (input) tTDIS tTDIH TDI tTCKcyc TCK Figure 2.95 Data transfer timing RZ/T2M Datasheet 2. Electrical Characteristics R01DS0383EJ0100 Rev.1.00 Mar 22, 2022 Page 119 of 127 |
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