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H5AN8G8NAFR-RDC Datasheet(PDF) 15 Page - Hynix Semiconductor |
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H5AN8G8NAFR-RDC Datasheet(HTML) 15 Page - Hynix Semiconductor |
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15 / 45 page ![]() Rev. 1.2 / Jul.2017 15 NOTE: 1. DIMM level Output test load condition may be different from above Figure 1 - Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement RESET CK_t/CK_c CKE CS ACT,RAS,CAS,WE A,BG,BA C ODT ZQ DQS_t/DQS_c DQ DM DDR4 SDRAM VSS VSSQ VDD VPP VDDQ IDD IPP IDDQ X Application specific memory channel environment Channel IO Powe Simulatin X Channel IO Power Number IDDQ TestLad IDDQ Simuaion IDDQ Measurement Correlation |
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