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ATO25F1GC-30EC Datasheet(PDF) 20 Page - List of Unclassifed Manufacturers

Part # ATO25F1GC-30EC
Description  3.3V 1G-BIT Serial NAND Flash Memory with Quad SPI
PDF  46 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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ATO25F1GC-30EC Datasheet(HTML) 20 Page - List of Unclassifed Manufacturers

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Sep.2013. Rev 0.5
1Gbit Serial NAND Flash Memory
8.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program, Block Erase, and
OTP program instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending
the instruction code, and then driving Chip Select (CS#) High.
Figure 8. Write Enable (WREN) instruction sequence
SCLK
CS#
0
1
2
3
4
5
6
7
Mode3
Mode0
Mode3
Mode0
Instruction (06h)
SI
SO
High Impedance



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