ATO25F1GC-30EC datasheet(8/46 Pages) ETC

8 / 46 page

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Sep.2013. Rev 0.5

1Gbit Serial NAND Flash Memory

1. General Description

The ATO25D1GA is 1G-bit with spare 32Mbit capacity. The device is offered in 3.3V power

supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage

market. The memory is divided into blocks that can be erased independently so it possible to

preserve valid data while old data is erased. The device contains 1024 blocks, composed by

64 pages consisting in two NAND structures of 32series connected Flash Cells. A program

operation can be performed in typical 200us on the 2048-bytes and an erase operation can be

performed in typical 2ms on a 128K-bytes block. Data in the page can be read out at 25ns

cycle time per byte. The on-chip write control automates all program and erase functions

including pulse repetition, where required, and internal verification and margining of data. Even

the write-intensive systems can take advantage of the ATO25D1GA

’s extended reliability of

100K program/erase cycles by providing ECC(Error Correction Code) with real time

mapping-out algorithm.

ATO25D1GA features a serial peripheral interface and software protocol allowing operation

on a simple 3-wire bus while it is in single I/O mode. The three signals are a clock input(SCLK),

a serial data input(SI), and a serial data output(SO). Serial access to the device is enabled by

CS# input. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and HOLD# pin

become SIO0 pin, SIO1 pin, SIO2 pin SIO3 pin for address/dummy bits input and data output.

The copy back function allows the optimization of defective blocks management : when a page

program operation fails the data can be directly programmed in another page inside the same

array section without the time consuming serial data insertion phase. The ATO25D1GA is an

optimum solution for large nonvolatile storage applications such as solid state file storage and

other portable applications requiring non-volatility.

After

program/erase

command

issued,

auto

program/erase

algorithms

which

program/erase and verify the specified page or sector/block locations will be executed. Up to

2Kbytes can be programmed at a time. Pages can be erased in groups of 128KB erase. To

provide user with ease of interface, a status register is included to indicate the status of the

chip. The status read command can be issued to detect completion status of a program or

erase operation via OIP bit. Advanced security features enhance the protection and security

functions, please see security features section for more details.

The ATO25D1GA supports JEDEC standard manufacturer and device identification with a

16Kbytes(8 pages) Secured OTP.

Figure 1. Logic Diagram

ATO25D1GA

SI(SIO0)

SCLK

CS#

W#(SIO2)

HOLD#(SIO3)

VCC

GND

SO(SIO1)

ATO25F1GC-30EC Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers

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