HT48C10 datasheet(19/59 Pages) HOLTEK

19 / 59 page

Bit No.

Label

Function

INTC

(0BH)

0EMI

Control the master (global) interrupt

(1= enabled; 0= disabled)

EEI

Control the external interrupt

(1= enabled; 0= disabled)

ET0I

Control the timer/event counter 0 interrupt

(1= enabled; 0= disabled)

3ET1I

Control the timer/event counter 1 interrupt (for the

HT48C50/HT48C70 only) (1= enabled; 0= disabled)

4EIF

External interrupt request flag

(1= active; 0= inactive)

T0F

Internal timer/event counter 0 request flag

(1= active; 0= inactive)

T1F

Internal timer/event counter 1 request flag (for the

HT48C50/HT48C70 only) (1= active; 0= inactive)

—

Unused bit, read as “0”

INTC register

event counter interrupt request flag (TF; bit 5 of

INTC), that is caused by a timer overflow. When

the interrupt is enabled, and the stack is not

full, and the TF bit is set, a subroutine call to

location 08H will occur. The related interrupt

request flag (TF) will be reset and the EMI bit

will be cleared to disable further interrupts.

The internal timer/event counter of the

HT48C50/HT48C70, is composed of two inter-

rupts, namely internal timer/event counter 0

interrupt and timer/event counter 1 interrupt.

The internal timer/event counter 0 interrupt is

initialized by setting the timer/event counter 0

interrupt request flag (T0F; bit 5 of INTC)

which is caused by a timer/event counter 0 over-

flow. After the interrupt is enabled, the stack is

not full, and the T0F bit is set, a subroutine call

to location 08H will occur. The related interrupt

request flag (T0F) will be reset and the EMI bit

be cleared to disable further interrupts. On the

other hand, the timer/event counter 1 interrupt

is operated in the same manner as the timer/

event counter 0. The related interrupt control

bits ET1I and T1F of the timer/event counter 1

are bit 3 and bit 6 of the INTC, respectively.

During the execution of an interrupt subroutine

of the four microcontrollers, other interrupt ac-

knowledgments are all held until the RETI in-

struction is executed or the EMI bit and the

related interrupt control bit are both set to 1

(when the stack is not full). To return from the

interrupt subroutine, the RET or RETI instruc-

tion may be invoked. The RETI will set the EMI

bit in order to enable an interrupt service

whereas the RET will not.

Interrupts that occur in an interval between the

rising edges of two consecutive T2 pulses are

serviced on the latter of the two T2 pulses if the

corresponding interrupts are enabled. In case of

simultaneous requests, the following table

shows the priority that is applied. These can be

masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

External interrupt

04H

Timer/event

counter 0 overflow

208H

Timer/event

counter 1 overflow

30CH

* Note: c applies only to the HT48C50/ HT48C70

HT48CXX/HT48RXX

25th May ’99

HT48C10 Datasheet(PDF) 19 Page - Holtek Semiconductor Inc

HT48C10 Datasheet(HTML) 19 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL