HT48C10 datasheet(22/59 Pages) HOLTEK

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nal reset, interrupt, external falling edge signal

on port A, or a WDT overflow. An external reset

may cause device initialization, and the WDT

overflow performs a “warm reset”. Examining the

TO and PD flags, the reason for chip reset is

determined. The PD flag is cleared by system

power-up or executing the CLR WDT instruction,

and is set by executing the HALT instruction. The

TO flag is set if the WDT time-out occurs, and

causes a wake-up that resets the PC and SP only.

The others maintain their original status.

The port A wake-up and interrupt methods can

be considered as a continuation of normal exe-

cution. Each bit in port A can be independently

selected to wake up the device by mask option.

Awakening from an I/O port stimulus, the pro-

gram will resume execution of the next instruc-

tion. On the other hand, awakening from an

interrupt, two sequences may happen. If the

related interrupt(s) is disabled or the inter-

rupt(s) is enabled but the stack is full, the pro-

gram will resume execution at the next

instruction. But if the interrupt is enabled and

the stack is not full, the regular interrupt re-

sponse takes place.

When wake-up event(s) occurs, it takes 1024

tSYS (system clock period) to resume normal

operation. That is to say, a dummy period is

inserted after the wake-up. If the wake-up re-

sults from an interrupt acknowledgment, the

actual interrupt subroutine execution will be

delayed by more than one cycle. But if the wake-

up results in the next instruction execution, the

instruction will execute immediately after the

dummy period is finished. If an interrupt re-

quest flag is set to “1” before entering the HALT

mode, the make-up function of the related inter-

rupt will be disabled.

To minimize power consumption, all the I/O

pins should be carefully managed before enter-

ing the HALT status.

Reset

There are three ways in which reset may occur:

• RES is reset during normal operation

• RES is reset during HALT

• WDT timeout is reset during normal operation

WDT time-out during the HALT is different

from other chip reset conditions, for it can per-

form a “warm reset” that resets only PC and SP

and leaves the other circuits at their original

state. Some registers remain unchanged during

any other reset conditions. Most of the registers

are reset to the “initial condition” when the

reset conditions are met. By examining the PD

flag and TO flag, the program distinguishes

between different “chip resets”.

RESET Conditions

RES reset during power-up

RES reset during normal

operation

RES wake-up HALT

Reset timing chart

Reset circuit

Reset configuration

HT48CXX/HT48RXX

25th May ’99

HT48C10 Datasheet(PDF) 22 Page - Holtek Semiconductor Inc

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