SH32F2601PSLASH032PR datasheet(13/370 Pages) SINOWEALTH

13 / 370 page

SH32F2601

7.3.1.3

Execution PSR

Execution PSR (EPSR) contains two overlapping areas:

Interrupt-Continual Instruction (ICI) area is used for loading multiple operations and storing multiple operation instructions

Execution status area is used for if-then (IT) instructions and T bit (Thumb status bit)

Interrupt-Continual Instruction (ICI) area

Multiple-load/store (LDM/STM) is interruptible. The ICI area of the EPSR is used to store the information required to

continue performing multiple loading and storing operations at the point of being interrupted.

If-Then instruction status area

The IT area of EPSR contains the execution status bits of If-Then instructions. EPSR cannot be accessed directly, to

modify EPSR, one of the following two events must occur:

An interrupt occurs when LDM or STM instructions are executed.

The If-Then instructions are executed

Note: ICI area and IT area overlap each other, so multiple-load/store operations with If-Then conditions are not

interruptible-continual.

b31

b30

b29

b28

b27

b26

b25

b24

b23

b22

b21

b20

b19

b18

b17

b16

Reserved

ICI/T

Reserved

b15

b14

b13

b12

b11

b10

ICT/IT

Reserved

Bit

Sign

Description

31 - 27

Reserved

15 - 12

ICI

Interrupt-Continual Instruction bits. If an interrupt occurs while executing an

LDM or STM operation, the LDM or STM operation is suspended. EPSR uses

[15:12] bit to store the index of the next register operand in the operation. After

the interrupt is responded, the processor returns to the register stored in

[15:12] and resumes operation. If the index is not in the register list of the

instruction, the processor continues to execute the LDM/STM operation using

the next register in the list (if any).

15 - 10:26 -

If-Then bits. They are the execution status bits of If-Then instruction,

containing the number of these instructions and their execution conditions.

The T bit is cleared using an interactive instruction, and the PC bit 0 written

here is zero. It can also be cleared by the exception POP operation (T bit

pushed in stack is 0). Executing an instruction when the T bit is 0 causes an

INVSTATE exception.

23 - 16

Reserved

9 - 0

Reserved

Base register update in LDM and STM operations

There are cases when an LDM or STM updates the base register:

When the instruction specifies base register write-back, the base register changes to the updated address. An abort

restores the original base value.

When the base register is in the register list of an LDM, and is not the last register in the list, the base register changes

to the loaded value.

An LDM/STM is restarted rather than continued if:

The instruction faults

The instruction is inside an IT

If an LDM has completed a base load, it is continued from before the base load.

Store xPSR bit

When entering an exception, the three status registers combined and stored into the stack.

SH32F2601P/032PR Datasheet(PDF) 13 Page - SINOWEALTH Electronic Ltd

SH32F2601P/032PR Datasheet(HTML) 13 Page - SINOWEALTH Electronic Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL