CS43131 datasheet(81/156 Pages) CIRRUS

81 / 156 page

DS1155F1

CS43131

5.13 Example Sequences

31 Configure DSD Path Signal Control 2

DSD Processor Path Signal Control 2.

0x70004

0x50

Reserved

DSD_PRC_SRC

DSD_EN

Reserved

DSD_SPEED

STA_DSD_DET

INV_DSD_DET

Set source of DSD processor to ASP

Enable DSD playback

Set DSD clock speed to 64•Fs

Static DSD detection disabled

Invalid DSD detection disabled

32 Configure DSD path Signal Control 3

DSD Processor Path Signal Control 3.

0x70006

0xC0

DSD_ZERODB

DSD_HPF_EN

Reserved

SIGCTL_DSDEQPCM

DSD_INV_A

DSD_INV_B

DSD_SWAP_CHAN

DSD_COPY_CHAN

The SACD 0–dB reference level (50%modulation

index) matches PCM 0-dB full scale.

Enable HPF in DSD processor

Function is disabled

33 Configure headphone output for 1.732 V rms

34 Configure Class H amplifier

Class H Control. 0xB0000

0x1E

Reserved

ADPT_PWR

HV_EN

EXT_VCPFILT

000

1 11

Output signal determines voltage level

High voltage mode enabled

Using internal VCPFILT source.

35 Set HP output to full scale

HP Output Control 1. 0x80000

0x30

HP_CLAMPA

HP_CLAMPB

OUT_FS

HP_IN_EN

HP_IN_LP

Reserved

+1dB_EN

Set headphone output to full scale (1.732 V rms)

36 Headphone detect

HP Detect. 0xD0000

0xC4

HPDETECT_CTRL

HPDETECT_INV

HPDETECT_RISE_DBC_TIME

HPDETECT_FALL_DBC_TIME

Reserved

0 0

HP detect enabled

HP detect input is not inverted

Tip Sense rising debounce time set to 0 ms

Tip sense falling debounce time set to 500 ms

37 Enable interrupts

38 Read Interrupt Status 1 register (0xF0000), Interrupt Status 2 register (0xF0001) and Interrupt Status 5 register (0xF0004) to clear sticky bits.

39 Enable headphone detect interrupts

Interrupt Mask 1. 0xF0010

0x99

DAC_OVFL_INT_MASK

HPDETECT_PLUG_INT_MASK

HPDETECT_UNPLUG_INT_MASK

XTAL_READY_INT_MASK

XTAL_ERROR_INT_MASK

PLL_READY_INT_MASK

PLL_ERROR_INT_MASK

PDN_DONE_INT_MASK

DAC_OVFL_INT is don't care

Enable HPDETECT_PLUG interrupt

Enable HPDETECT_UNPLUG interrupt

XTAL_READY_INT is don't care

XTAL_ERROR_INT is don't care

PLL_READY interrupt already enabled

PLL_ERROR interrupt already enabled

PDN_DONE_INT is don't care

40 Enable ASP interrupts

Interrupt Mask 2. 0xF0011

0x07

ASP_OVFL_INT_MASK

ASP_ERROR_INT_MASK

ASP_LATE_INT_MASK

ASP_EARLY_INT_MASK

ASP_NOLRCK_INT_MASK

Reserved

111

Enable ASP_OVFL interrupt

Enable ASP_ERROR interrupt

Enable ASP_LATE interrupt

Enable ASP_EARLY interrupt

Enable ASP_NOLRCK interrupt

41 Enable DSD and DoP interrupts

Interrupt Mask 5. 0xF0014

0x01

DSD_STUCK_INT_MASK

DSD_INVAL_A_INT_MASK

DSD_INVAL_B_INT_MASK

DSD_SILENCE_A_INT_MASK

DSD_SILENCE_B_INT_MASK

DSD_RATE_ERROR_INT_MASK

DOP_MRK_DET_INT_MASK

DOP_ON_INT_MASK

Enable DSD_STUCK interrupt

Enable DSD_INVAL_A interrupt

Enable DSD_INVAL_B interrupt

Enable DSD_SILENCE_A interrupt

Enable DSD_SILENCE_B interrupt

Enable DSD_RATE_ERROR interrupt

Enable DOP_MRK_DET interrupt

Disable DOP_ON interrupt

42 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000).

43 Set MCLK source and frequency

System Clocking Control. 0x10006

0x05

Reserved

MCLK_INT

MCLK_SRC_SEL

0000 0

MCLK Frequency is set to 22.5792 MHz

MCLK Source is set to PLL

44 Wait for at least 150 µs.

Example 5-9. DoP Playback with PLL (Cont.)

STEP

TASK

VALUE

DESCRIPTION

CS43131 Datasheet(PDF) 81 Page - Cirrus Logic

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