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CS43131 Datasheet(PDF) 26 Page - Cirrus Logic |
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CS43131 Datasheet(HTML) 26 Page - Cirrus Logic |
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26 / 156 page  26 DS1155F1 CS43131 3 Characteristics and Specifications 1.Serial audio input interface timing 2.Phase modulation mode serial audio input interface timing Table 3-22. I2C Slave Port Characteristics Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to ground; VL = 1.8 V; inputs: Logic 0 = GNDA = 0 V, Logic 1 = VL; TA = +25°C; SDA load capacitance equal to maximum value of CB = 400 pF; minimum SDA pull-up resistance, RP(min).1 Table 3-1 describes some parameters in detail. All specifications are valid for the signals at the pins of the CS43131 with the specified load capacitance. 1.The minimum RP value (resistor shown in Fig. 2-1) is determined by using the maximum level of VL, the minimum sink current strength of its respective output, and the maximum low-level output voltage VOL. The maximum RP value may be determined by how fast its associated signal must transition (e.g., the lower the value of RP, the faster the I2C bus is able to operate for a given bus load capacitance). See I²C bus specification referenced in Section 13. Parameter 2 2.All timing is relative to thresholds specified in Table 3-13, VIL and VIH for input signals, and VOL and VOH for output signals. Symbol 3 Minimum Maximum Units SCL clock frequency fSCL —1000 kHz Clock low time tLOW 500 — ns Clock high time tHIGH 260 — ns Start condition hold time (before first clock pulse) tHDST 260 — ns Setup time for repeated start tSUST 260 — ns Rise time of SCL and SDA Standard Mode Fast Mode Fast Mode Plus tRC — — — 1000 300 120 ns ns ns Fall time of SCL and SDA Standard Mode Fast Mode Fast Mode Plus tFC — — — 300 300 120 ns ns ns Setup time for stop condition tSUSP 260 — ns SDA setup time to SCL rising tSUD 50 — ns SDA input hold time from SCL falling 4 tHDDI 0— ns Output data valid (Data/Ack) 5 Standard Mode Fast Mode Fast Mode Plus tVDDO — — — 3450 900 450 ns ns ns Bus free time between transmissions tBUF 500 — ns SDA bus capacitance SCL frequency = 1 MHz, VL = 1.8 V SCL frequency ≤ 400 kHz CB — — 340 400 pF pF SCL/SDA pull-up resistance 1 VL = 1.8 V RP 350 — Ω Pulse width of spikes to be suppressed tPS —50 ns Switching time between RCO and MCLK_INT 6 — 150 — µs Power-up delay (delay before I2C can communicate after RESET released) tPUD 1500 — µs DSDCLK DSDA, DSDB tSDLRS tSDH tSCLKL tSCLKH DSDCLK (128 •Fs) DSDCLK (64 •Fs) DSDA, DSDB tDPM tDPM |
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