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TC35679FSG Datasheet(PDF) 42 Page - Toshiba Semiconductor |
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TC35679FSG Datasheet(HTML) 42 Page - Toshiba Semiconductor |
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42 / 45 page ![]() TC35679FSG-002 2018-01-17 42 6. System Configuration Example An example of system configuration is shown in the following figures. 6.1. In case of Host CPU connection Host interface=UART and 26 MHz Reference Clock= XOSC Connection. XOSC (32.768 kHz) of the dotted line enclosure is unnecessary when the external input (HOST common use) is chosen. The connections of GPIO and SWD are the example of when they are not in use. Figure 6-1 Example of TC35679FSG system configuration (HOST CPU connection) HOST I/F UART_RX UART_TX WakeUP0 RESETX VDD TC35679FSG 18 VBAT 1 VDDIO1 19 LX 14 VDDCORE1 15 VDDCORE2 4 TMODE 5 VPGM 13 VSSX 20 VSSDC 27,FIN VSSD1,VSSD2 7 RFIO 8 VSSA 9 TRTEST1 10 TRTEST2 26 GPIO10 30 GPIO3 29 GPIO4 28 GPIO9 35 GPIO11 34 GPIO12 40 GPIO1 16 GPIO2 25 GPIO13 2 GPIO25 31 GPIO0 39 38 37 36 GPIO5 3 RESETX 21 SLPXOIN 22 SLPXOOUT 12 XOOUT 11 XOIN 32.768KHz 2 X2 1 X1 ANT Coaxial Connecter VDD BAT_1 2 1 SleepClockIN 23 VDDIO2 VDD GPIO6 GPIO7 GPIO8 WakeUP1 33 GPIO15 24 GPIO14 6 VSSRFIO 32 SWDCLK 17 SWDIO |
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