MPC8540 datasheet(190/1302 Pages) FREESCALE

190 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

4-4

Freescale Semiconductor

Reset, Clocking, and Initialization

4.3.1.1

Accessing Configuration, Control, and Status Registers

The configuration, control, and status registers are memory mapped. The set of configuration,

control, and status registers occupies a 1-Mbyte region of memory. Their location is programmable

using the CCSR base address register (CCSRBAR). The default base address for the

configuration, control, and status registers is 0xFF70_0000 (CCSRBAR = 0x000F_F700).

CCSRBAR itself is part of the local access block of CCSR memory, which begins at offset 0x0

from CCSRBAR. Because CCSRBAR is at offset 0x0 from the beginning of the local access

registers, CCSRBAR always points to itself. The contents of CCSRBAR are broadcast internally

in the MPC8540 to all functional units that need to be able to identify or create configuration

transactions.

4.3.1.1.1

Updating CCSRBAR

Updates to CCSRBAR that relocate the entire 1-Mbyte region of configuration, control, and status

registers, requires special treatment. The effect of the update must be guaranteed to be visible by

the mapping logic before an access to the new location is seen. To make sure this happens, these

guidelines should be followed:

•

CCSRBAR should be updated during initial configuration of the device when only one host

or controller has access to the device.

– If the boot sequencer is being used to initialize, it is recommended that the boot

sequencer set CCSRBAR to its desired final location.

– If an external host on PCI or RapidIO is configuring the device, it should set

CCSRBAR to the desired final location before the e500 core is released to boot.

– If the e500 core is initializing the device, it should set CCSRBAR to the desired final

location before enabling other I/O devices to access the device.

•

When the e500 core is writing to CCSRBAR, it should use the following sequence:

– Read the current value of CCSRBAR using a load word instruction followed by an

isync. This forces all accesses to configuration space to complete.

– Write the new value to CCSRBAR.

Table 4-4. Local Configuration Control Register Map

Local Memory

Offset (Hex)

Access

Reset

Section/Page

0x0_0000

CCSRBAR—Configuration, control, and status registers

base address register

R/W

0x000F_F700

4.3.1.1.2/4-5

0x0_0008

ALTCBAR—Alternate configuration base address register

R/W

0x0000_0000

4.3.1.2.1/4-6

0x0_0010

ALTCAR—Alternate configuration attribute register

R/W

0x0000_0000

4.3.1.2.2/4-6

0x0_0020

BPTR—Boot page translation register

R/W

0x0000_0000

4.3.1.3.1/4-8

MPC8540 Datasheet(PDF) 190 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 190 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL