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STM32W108HB Datasheet(PDF) 107 Page - STMicroelectronics

Part # STM32W108HB
Description  High-performance, IEEE 802.15.4 wireless system-on-chip with up to 256 Kbytes of embedded Flash memory
PDF  278 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32W108HB Datasheet(HTML) 107 Page - STMicroelectronics

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Serial interfaces
Doc ID 16252 Rev 14
107/278
SPI - Master
SC1MOSI alternate
output (push-pull)
SC1MISO input
SC1SCLK alternate
output (push-pull);
special SCLK mode
(not used)
SPI - Slave
SC1MISO alternate
output (push-pull)
SC1MOSI input
SC1SCLK input
SC1nSSEL input
I2C - Master
SC1SDA alternate
output (open-drain)
SC1SCL alternate
output (open-drain)
(not used)
(not used)
UART
TXD alternate
output (push-pull)
RXD input
nCTS input (1)
nRTS alternate
output (push-pull)
(1)
SPI - Master
SC2MOSI
Alternate Output
(push-pull)
SC2MISO Input
SC2SCLK
Alternate Output
(push-pull), special
SCLK mode
(not used)
SPI - Slave
SC2MOSI
Alternate Output
(push-pull)
SC2MISO Input
SC2SCLK Input
SC2nSSEL Input
I2C - Master
(not used)
SC2SDA Alternate
Output (open-drain)
SC2SCL Alternate
Output (open-drain)
(not used)
9.3
SPI master mode
The SPI master controller has the following features:
●
Full duplex operation
●
Programmable clock frequency (6 MHz max. for STM32W108xB and 12 MHz max for
STM32W108CC and STM32W108CZ)
●
Programmable clock polarity and phase
●
Selectable data shift direction (either LSB or MSB first)
●
Receive and transmit FIFOs
●
Receive and transmit DMA channels
The SPI master controller uses the three signals:
●
MOSI (Master Out, Slave In) - outputs serial data from the master
●
MISO (Master In, Slave Out) - inputs serial data from a slave
●
SCLK (Serial Clock) - outputs the serial clock used by MOSI and MISO
The GPIO pins used for these signals are shown in Table 21. Additional outputs may be
needed to drive the nSSEL signals on slave devices.
Table 19.
SC1 GPIO usage and configuration
Interface
PB1
PB2
PB3
PB4
1.
used if RTS/CTS hardware flow control is enabled.
Table 20.
SC2 GPIO usage and configuration
Interface
PA0
PA1
PA2
PA3



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