47L64 datasheet(2/29 Pages) MICROCHIP

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2019-2020 Microchip Technology Inc.

Preliminary

DS20006168B-page 2

47L64

General Description

The Microchip Technology Inc. 47L64 serial EERAM

has an SRAM memory core with hidden EEPROM

backup. The device can be treated by the user as a full

symmetrical read/write SRAM. Backup to EEPROM is

handled by the device on any power disrupt, so the

user can effectively view this device as an SRAM that

never loses its data.

The device is structured as a 64-Kbit SRAM with

EEPROM backup in each memory cell. The SRAM is

organized as 8,192 x 8 bits and uses the I2C serial

interface. The I2C bus uses two signal lines for

communication: clock input (SCL) and data (SDA).

Access to the device is controlled through a chip

address and address pins, allowing up to four devices

to share the same bus.

The SRAM is a conventional serial SRAM: it allows

symmetrical reads and writes and has no limits on cell

usage. The backup EEPROM is invisible to the user

and cannot be accessed by the user independently.

The device includes circuitry that detects VCC

dropping below a certain threshold, shuts its

connection to the outside environment, and transfers

all SRAM data to the EEPROM portion of each cell for

safe keeping. When VCC returns, the circuitry

automatically returns the data to the SRAM and the

user’s interaction with the SRAM can continue with the

same data set.

Block Diagram

Powering the Device During SRAM to

EEPROM Backup (VCAP)

A small capacitor (typically 22 µF) is required for the

proper operation of the device. This capacitor is placed

between VCAP (pin 1) and the system VSS (see Normal

Device Operation). When power is first applied to the

device, this capacitor is charged to VCC through the

device (see Normal Device Operation). During normal

SRAM operation, the capacitor remains charged to

VCC and the level of system VCC is monitored by the

device. If system VCC drops below a set threshold, the

device interprets this as a power-off or brown-out

event. The device suspends all I/O operation, shuts off

its connection with the VCC pin, and uses the saved

energy in the capacitor to power the device through the

VCAP pin as it transfers all SRAM data to EEPROM

(see Vcc Power-Off Event). On the next power-up of

VCC, the data is transfered back to SRAM, the

capacitor is recharged, and the SRAM operation

continues.

Normal Device Operation

VCC Power-Off Event

Power

I2C Control Logic

Memory Address

and Data Control

Logic

and Address

VCC

Control

Block

VCAP

Decoder

EEPROM

RECALL

STORE

SDA

SCL

SRAM

8K x 8

CC Monitor

Normal

SRAM

Operation

CC (pin 8)

CAP (pin

)

VCAP

Charged to V

SS (pin 4)

System V

Automatic

Backup

SRAM

SRAM to

EEPROM

Transfer

EEPROM

CC (pin 8)

System V

CAP (pin

)

VCAP

Temporary V

SS (pin 4)

System V

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