47L64 datasheet(6/29 Pages) MICROCHIP

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2019-2020 Microchip Technology Inc.

Preliminary

DS20006168B-page 6

47L64

2.0

PIN DESCRIPTION

The description of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

2.1

A1, A2 Chip Address Inputs

The A1, A2 inputs are used by the 47L64 for multiple

device operation. The levels on these inputs are

compared with the corresponding Chip Select bits in

the slave address. The chip is selected if the

comparison is true.

Up to four devices may be connected to the same bus

by using different Chip Select bit combinations. These

pins are not pulled up or down internally, so they must

be externally connected to VCC or VSS.

2.2

Serial Data (SDA)

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open-

drain terminal, therefore, the SDA bus requires a pull-

up resistor to VCC (typical 10 k for 100 kHz, 2 kfor

400 kHz and 1 MHz).

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

2.3

Serial Clock (SCL)

This input is used to synchronize the data transfer from

and to the device.

2.4

Write-Protect Input

When the WP pin is set high, then writes within the

upper 1/4 of memory will not be allowed. Attempts to

write in that protected region over the I2C bus will return

an ACK (Acknowledge) for the WRITE instruction and

address byte portions of the command, and will also

return an ACK (Acknowledge) for the data portion of

the command, despite the fact that no data will be

written. See Table 4-1. The WP pin has no effect on

random or sequential read operations. If left floating,

this pin is internally pulled low.

Name

8-Lead SOIC

8-Lead TDFN(1)

Function

VCAP

External Capacitor

Chip Select Input

Vss

Ground

SDA

Serial Data

SCL

Serial Clock

Write Protect

Vcc

2.7V to 3.6V

Note 1: The exposed pad on the TDFN package can be connected to VSS or left floating.

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